1. Field of the Invention
The invention relates generally to digital bit-serial data transfer between one device and another, and the verification of the integrity of such a transfer by having the transmitted data bit-serially returned to the originating device. The invention specifically relates to a digital logic device which, responsively to a single software initiated operation, allows the simultaneous loading and verification of a control store in a remotely situated device via a bit-serial digital SCAN loop.
2. Description of the Prior Art
It is current computer design practice to employ microcode designs in many of the central complex units of medium to large scale digital computer systems. These microcoded designs are controlled by data stored in local memories called control stores. It is common practice to utilize an inexpensive, separate, minicomputer-type device to load the various control stores of the various central complex units within a computer system. Such a minicomputer-type device may be identified as a SYSTEM SUPPORT PROCESSOR, or SSP.
A second task commonly performed by the same SSP which loads the control store of central complex units within a computer system is the control of scan/set networks within such central complex units. The scan/set networks within each central computer complex allows the SSP to read or write the state of all storage elements within such networks for the purpose of functional tests. It is also known to utilize a scan/set network for the loading of the control stores within the various central complex units of the computer system.
The prior art procedure by which the control stores of the central complex units of a computer system have been loaded via the scan/set network mechanism controlled from a SYSTEMS SUPPORT PROCESSOR is as follows. The SSP obtains the data to be written into the control store of the remote central complex unit from a data source, such as a peripheral floppy disk drive, and normally emplaces this data within an SSP internal buffer memory store, such as a RAM. Next, the data may be directly or indirectly written into the remote control store, usually a RAM, of the central complex unit via the bit-serial data transmission capability of the scan/set network. After the entirety of the control store is loaded, the written contents of such control store are next read back to the SSP via the selfsame scan/set network. Finally, the data read from the CONTROL STORE, via the scan/set network, is compared with the data written to such control store, via the scan/set network, within the SSP in order to verify the integrity of the process.
The procedure of writing a remote control store, reading the contents of such control store, and comparing the read content to the written content for purposes of verification, was acceptable when only a few such remote central complex units existed, and/or the control stores within such central complex units were of modest bit length. As the number and size of control stores, nominally RAMs, in computer systems is growing larger with successive system generations, the time of loading all such control stores during system initialization has grown unacceptably long. The subject invention of this disclosure will deal with this problem by selectively either performing the writing and reading of the control store (both via the scan/set network) substantially simultaneously and concurrently, or by selectively performing both the writing of the control store, the reading of the control store, and the verification of the data read against the data written--all three steps--substantially simultaneously as concurrent operations.
As subsidiary aspects of the present invention wherein the loading plus the reading plus (selectively) the verifying of a control store within a central complex unit may be accomplished in time overlap by a SYSTEMS SUPPORT PROCESSOR both writing and reading such control store within such central complex unit via a scan/set network, it will become evident that the present invention exhibits versatility as to the addressable locations, and variable bit lenths, of the control stores so loaded. Specifically, it is known in the art that a central digital logic device, a SYSTEM SUPPORT PROCESSOR, managing a scan/set network is able to, via an address word called a HEADER quantity, addressably select amongst a number of central complex units interconnected on one such scan/set network. Specifically, it is further known in the prior art that the central scan/set network controlling digital logic device, the SYSTEM SUPPORT PROCESSOR, is able to addressably select, also by the information contained within such HEADER word, a single one scan/set test loop, called a single STRING, from amongst a number of such loops existing within each central complex unit device. Finally, it is also known that the central scan/set network controlling digital logical device, the SYSTEM SUPPORT PROCESSOR, may, having identified a particular scan/set test loop within a particular central complex unit device, proceed to deal with such scan/set test loop in rough accordance with its individual bit length. Normally, and when normally accomplished under microprocessor control, such manipulation of the scan/set test loops, the STRINGS, is granularized in accordance with some basic number of bits, nominally 8-bits as comprise a byte, which is the basic quantum of communication to and from such scan/set test loop via such scan/set network. In other words, the scan/set central network controlling element, the SYSTEM SUPPORT PROCESSOR, will normally addressably select and deal with scan/set test loops which are in bit-length multiples of 8-bits; e.g. 136-bits, or 168-bits, as might be respectively associated with two individually addressable STRINGS. When the number of bits, representing scan/set testable stored latches within a scan/set test loop, is not an integer number in modulus eight, then additional "zero", or placeholding, bits are normally transferred as part of the scan/set test process and/or the control stores loading process. The present invention overcomes this limitation of dealing with individually addressable bit strings of a bit-length modulus greater than one (1).